As a passionate VLSI Frontend Design enthusiast, I bring hands-on experience in digital designing, Verilog, and SystemVerilog. My expertise is complemented by proficiency in industry-standard tools and the UVM methodology. I have a strong academic foundation with a B.Tech in Electronics and Computer Engineering from MGM University, where my coursework focused on Digital System Design and VLSI Design.
I've honed my skills through multiple industry-level projects and a traineeship. During my time as a Design Verification Trainee at VLSI GURU, I refined core concepts in Advanced Digital Design, including timing analysis and FSMs. I also gained proficiency in Linux-based workflows using tools like Synopsys Verdi and Synopsys VCS.
My projects demonstrate my ability to apply these skills to real-world challenges. For example, I developed an AXI Universal Verification Component (UVC) using SystemVerilog and UVM, which included creating a layered testbench architecture and a dual scoreboard for interleaved and out-of-order transfers. I also designed and verified an AMBA APB protocol system in Verilog and an asynchronous FIFO, achieving 100% code and functional coverage on both.
Beyond my technical work, I am a winner of the Smart India Hackathon 2023 and a finalist in the IN-SPACE CANSAT India Competition 2024. I also contribute to the VLSI community as an author, publishing technical blogs on digital design and verification methodologies. These experiences highlight my problem-solving skills, teamwork, and critical thinking.
Jan 2025 - Spt 2025
• Refined core concepts in Advanced Digital Design, including FSMs, timing diagrams and analysis, combinational circuits and sequential circuits.
• Built RTL designs using Verilog HDL, applying best practices and debugging with ModelSim and GVIM.
• Developed SystemVerilog-based testbenches, practicing simulation workflows on EDA Playgrounds QuestaSim.
• Mastered UVM methodology, constructing modular testbenches using predefined classes, macros, and reusable components with UVC development.
• Gained proficiency in Linux for server-based workflows, using tools like Synopsys Verdi, Synopsys VCS, and Siemens QuestaSim for simulation and waveform analysis with Git for version control.
Oct 2021 - June 2025
Pursued a Bachelor of Technology in Electronics and Computer Engineering. This program has provided me with a solid foundation in both electronics and computer science, with a focus on Digital System Design and VLSI Design. Achieved a CGPA of 8.39.
July 2019 - may 2021
I completed my Higher Secondary Education at Vidhyadham Jr. Science College in Maharashtra, achieving a final percentage of 94.00%.
I am eager to apply my knowledge and practical expertise to solve complex challenges in the VLSI industry.
I have hands-on experience in RTL designing using Verilog, building functional and efficient digital circuits. My work includes the design of a parametrizable Single Port RAM and a Single Cycle RISC-V Processor.
I have mastered the UVM Methodology for creating robust and reusable testbenches. I apply this methodology to develop modular verification environments, ensuring comprehensive and systematic testing of complex designs.
I specialize in Design Verification, ensuring the functional correctness and compliance of digital designs. I create comprehensive test cases and use techniques like assertion-based verification to validate designs.
I have experience in verifying industry-standard protocols, including AXI , AHB, and APB. My projects demonstrate my ability to implement complex verification environments with features like dual scoreboards for handling interleaved transactions.
I leverage Python scripting to automate design and verification tasks, improving efficiency and reducing manual effort. This includes tasks such as test case generation and data processing.
I am proficient with a range of industry-standard EDA tools for simulation and waveform analysis. My experience includes using Synopsys VCS, QuestaSim, Synopsys Verdi, and ModelSim in Linux-based workflows.
Explore my portfolio of industry-level projects. Each one demonstrates my hands-on experience in VLSI design and verification.
UVM, SystemVerilog, Synopsys VCS, Verdi, GVIM
UVM, SystemVerilog, Synopsys VCS, Verdi, GVIM
UVM, SystemVerilog, Verilog, QuestaSim, GVIM
UVM, SystemVerilog, Verilog, QuestaSim, GVIM
Verilog, ModelSim, GVIM
This project implements an Advanced Peripheral Bus (APB) protocol system, including an APB master, two APB slaves, and a top module integrating them. The system is designed according to the AMBA APB specification, supporting read and write operations with error handling and slave selection based on address decoding. A comprehensive testbench is provided to validate the system's functionality through various test cases.
Verilog, EDA Playground, GVIM
Verilog, Xilinx Vivado, VStudio Code
This project demonstrates the integration of the inbuilt 3-axis accelerometer (ADXL362) on the Nexys A7-50T FPGA board. The accelerometer data is read using SPI communication and visualized through 7-segment displays and LEDs. The Verilog-based design handles SPI communication, data processing, and display control, providing a practical example of FPGA-based sensor interfacing.
Verilog, Xilinx Vivado, VStudio Code
I'm always open to new opportunities and collaborations. Whether you have an idea for a project, a job opening, or just want to discuss the latest in VLSI design and verification, I'm happy to connect. Let's work together to create something impactful. Email Me.
